Hidden Bibliographic Details
| Other authors / contributors: | Hill, Mark D. (Mark Donald)
Wood, David A.
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| ISBN: | 9781608455652 (electronic bk.)
9781608455645 (pbk.)
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| Notes: | Part of: Synthesis digital library of engineering and computer science.
Series from website.
Includes bibliographical references.
Abstract freely available; full-text restricted to subscribers or individual document purchasers.
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Also available in print.
Mode of access: World Wide Web.
System requirements: Adobe Acrobat Reader.
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| Summary: | Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high level concepts as well as specific, concrete examples from real-world systems.
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| Standard no.: | 10.2200/S00346ED1V01Y201104CAC016
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