Low-noise low-power design for phase-locked loops : multi-phase high-performance oscillators /

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Bibliographic Details
Author / Creator:Zhao, Feng, author.
Imprint:Cham : Springer, 2015.
©2015
Description:1 online resource (xiii, 96 pages) : illustrations (some color)
Language:English
Subject:
Format: E-Resource Book
URL for this record:http://pi.lib.uchicago.edu/1001/cat/bib/11090049
Hidden Bibliographic Details
Other authors / contributors:Dai, Fa Foster, author.
ISBN:9783319122007
3319122002
9783319121994
3319121995
Digital file characteristics:text file PDF
Notes:Includes bibliographical references.
Online resource; title from PDF title page (SpringerLink, viewed February 2, 2015).
Summary:This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation.℗ℓ The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage.℗ℓ Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.℗ℓ
Other form:Original 3319121995 9783319121994
Standard no.:10.1007/978-3-319-12200-7