Hardware IP security and trust /
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| Imprint: | Cham, Switzerland : Springer, 2017. |
|---|---|
| Description: | 1 online resource |
| Language: | English |
| Subject: | |
| Format: | E-Resource Book |
| URL for this record: | http://pi.lib.uchicago.edu/1001/cat/bib/11270678 |
Table of Contents:
- Acknowledgements; Contents; Abbreviations (Acronyms); Part I Introduction; 1 Security and Trust Vulnerabilities in Third-Party IPs; 1.1 Introduction; 1.2 Design and Validation of SoCs; 1.3 Security and Trust Vulnerabilities in Third-Party IPs; 1.4 Trustworthy SoC Design Using Untrusted IPs; 1.5 Book Organization; References; Part II Trust Analysis; 2 Security Rule Check; 2.1 Introduction; 2.2 Security Assets and Attack Models; 2.2.1 Asset; 2.2.2 Potential Access to Assets; 2.2.3 Potential Adversary for Intentional Attacks; 2.3 DSeRC: Design Security Rule Check; 2.3.1 Vulnerabilities.
- 2.3.1.1 Sources of Vulnerabilities2.3.1.2 Vulnerabilities at Different Abstraction Levels; 2.3.2 Metrics and Rules; 2.3.3 Workflow of DSeRC Framework; 2.4 Development of DSeRC Framework; 2.4.1 Vulnerabilities, Metrics, and Rules; 2.4.2 Tool Development; 2.4.3 Development of Design Guidelines for Security; 2.4.4 Development of Countermeasure Techniques; 2.5 Conclusion; References; 3 Digital Circuit Vulnerabilities to Hardware Trojans; 3.1 Introduction; 3.2 The Gate-Level Design Vulnerability Analysis Flow; 3.3 The Layout-Level Design Vulnerability Analysis Flow; 3.3.1 Cell and Routing Analyses.
- 3.3.2 Net Analysis3.4 Trojan Analyses; 3.5 Conclusions; References; 4 Code Coverage Analysis for IP Trust Verification; 4.1 Introduction; 4.2 SoC Design Flow; 4.3 Hardware Trojan Structure; 4.4 Related Work; 4.5 A Case Study for IP Trust Verification; 4.5.1 Formal Verification and Coverage Analysis; 4.5.2 Techniques for Suspicious Signals Reduction; 4.5.2.1 Phase 1: Test Bench Generation and Suspicious Signal Identification; 4.5.2.2 Phase 2: Suspicious Signals Analysis; 4.6 Simulation Results; 4.6.1 Benchmark Setup; 4.6.2 Impact of Test Bench on Coverage Analysis.
- 4.6.3 Reducing the Suspicious Signals4.6.4 Trojan Coverage Analysis; 4.7 Conclusion; References; 5 Analyzing Circuit Layout to Probing Attack; 5.1 Introduction; 5.2 Microprobing Attack Techniques; 5.2.1 Essential Steps in a Probing Attack; 5.2.2 Microprobing Through Milling; 5.2.3 Back-Side Techniques; 5.2.4 Other Related Techniques; 5.3 Protection Against Probing Attacks; 5.3.1 Active Shields; 5.3.2 Techniques to Attack and Secure Active Shields; 5.3.2.1 Routing Overhead; 5.3.2.2 Stuck on Top Metal Layer; 5.3.3 Other Antiprobing Designs; 5.3.4 Summary on Antiprobing Protections.
- 5.4 Layout-Based Evaluation Framework5.4.1 Motivation; 5.4.2 Assessment Rules; 5.4.3 State-of-the-Art Active Shield Model; 5.4.4 Impact of Milling Angle upon Effect of Bypass Attack; 5.4.5 Algorithm to Find Exposed Area; 5.4.6 Discussions on Applications of Exposed Area Algorithm; 5.5 Conclusion; References; 6 Testing of Side-Channel Leakage of Cryptographic Intellectual Properties: Metrics and Evaluations; 6.1 Introduction; 6.2 Preliminaries on Statistical Testing and Testing of Hypothesis; 6.2.1 Sampling and Estimation; 6.2.2 Some Statistical Distributions.