Radiation hardened CMOS integrated circuits for time-based signal processing /
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Author / Creator: | Prinzie, Jeffrey, author. |
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Imprint: | Cham, Switzerland : Springer, 2018. |
Description: | 1 online resource |
Language: | English |
Series: | Analog circuits and signal processing, 1872-082X Analog circuits and signal processing series. |
Subject: | |
Format: | E-Resource Book |
URL for this record: | http://pi.lib.uchicago.edu/1001/cat/bib/11654539 |
Table of Contents:
- Intro; Preface; Contents; List of Abbreviations and Symbols; Abbreviations; Symbols; List of Figures; List of Tables; 1 Radiation Effects in CMOS Technology; 1.1 Radiation and Its Interaction with Matter; 1.1.1 Direct Ionization; 1.1.2 Electromagnetic Radiation; 1.1.3 Neutrons; 1.1.4 Effects on Semiconductors; 1.2 Total Ionizing Dose Effects; 1.2.1 Basic Charge Trapping in CMOS Transistors; 1.2.2 Narrow Channel Transistors; 1.2.3 Short Channel Transistors; 1.2.4 Enclosed Layout Transistors; 1.2.5 Experimental Results; 1.3 Single-Event Effects; 1.3.1 Basic Mechanism.
- 1.3.2 Effect on nmos and pmos Devices1.3.3 SET, SEU, SEL; 1.3.4 SEU Mitigation Techniques in Digital Blocks; 1.3.5 Charge Sharing; 1.4 Simulation Methods to Simulate Radiation Effects; 1.4.1 Simulation of TID Effects on Circuits; 1.4.2 Simulation of Single-Event Effects on Circuits; 1.5 Conclusion; 2 Time-Domain Signal Processing; 2.1 Introduction; 2.2 Time-to-Digital Converters; 2.3 Applications of Time-Based Circuits; 2.3.1 High-Energy Physics; 2.3.2 PET Scanners; 2.3.3 Time-of-Flight LIDAR; 2.3.4 All-Digital PLLs; 2.4 TDC Circuits; 2.4.1 Performance Parameters.
- 2.4.1.1 Single-Shot Precision2.4.1.2 Linearity; 2.4.1.3 Gain Error; 2.4.1.4 Conversion Speed; 2.4.2 Delay-Line Based TDCs; 2.4.3 Sub-gate Delay-Line TDCs; 2.4.3.1 Vernier Architecture; 2.4.3.2 Local Phase Interpolation; 2.4.3.3 Parallel TDCs; 2.4.4 Delay-Locked Loops; 2.4.5 Multi-Stage TDCs; 2.4.5.1 Coarse-Fine TDCs; 2.4.5.2 Pipelined TDCs; 2.4.6 Looped TDCs; 2.4.7 Oversampling TDCs; 2.4.7.1 Gated Ring-Oscillator; 2.4.8 Other TDC Architectures; 2.4.8.1 Stochastic TDCs; 2.4.8.2 Wave Union Launcher; 2.4.9 Input Path; 2.5 Conclusion; 3 Clock Synthesizers; 3.1 Introduction; 3.2 Phase Locked Loops.
- 3.2.1 Phase-Domain Model3.2.2 Components for Charge-Pump PLLs; 3.2.2.1 Phase Detector; 3.2.2.2 Phase-Frequency Detector; 3.2.2.3 Bang-Bang Phase Detector; 3.2.2.4 Charge-Pump: Loop Filter; 3.2.2.5 Divider; 3.3 Oscillators; 3.3.1 Oscillation Criteria; 3.3.2 LC-Oscillators; 3.3.3 Ring-Oscillators; 3.4 Jitter and Phase-Noise; 3.4.1 Definitions; 3.4.2 Phase Noise in LC-Tank Oscillators; 3.4.2.1 Linear Calculation; 3.4.2.2 Impulse Sensitive Function; 3.4.3 Phase Noise Spectrum of an Oscillator; 3.5 Phase-Noise in PLLs; 3.5.1 Noise Transfer Function; 3.5.2 Reference Clock Phase Noise.
- 3.5.3 Charge-Pump: Loop Filter3.5.4 Oscillator; 3.5.5 Spurious Tones; 3.6 Performance Parameters; 3.7 Conclusion; 4 Single Shot Time-to-Digital Converters; 4.1 Introduction; 4.2 TDC System Level Architecture; 4.2.1 Self-Calibration Loop Implemented by a DLL; 4.2.2 System Architecture with Double Phase Detector; 4.2.3 TDC Timing Generator Linearity; 4.2.4 Channeling and Basic Readout Interfaces; 4.3 Low Offset Bang-Bang Phase Detector; 4.3.1 Origin of Static Phase Offsets; 4.3.2 Removing Static Phase Offsets; 4.3.3 Circuit Implementations; 4.4 Experimental Results; 4.5 Conclusion.