Embedded deep learning : algorithms, architectures and circuits for always-on neural network processing /
Saved in:
| Author / Creator: | Moons, Bert, author. |
|---|---|
| Imprint: | Cham : Springer, 2018. ©2019 |
| Description: | 1 online resource (xvi, 206 pages) |
| Language: | English |
| Subject: | |
| Format: | E-Resource Book |
| URL for this record: | http://pi.lib.uchicago.edu/1001/cat/bib/11746434 |
Table of Contents:
- Intro; Preface; Acknowledgments; Contents; Acronyms; 1 Embedded Deep Neural Networks; 1.1 Introduction; 1.2 Machine Learning; 1.2.1 Tasks, T; 1.2.2 Performance Measures, P; 1.2.3 Experience, E; 1.2.3.1 Supervised Learning; 1.2.3.2 Unsupervised Learning; 1.3 Deep Learning; 1.3.1 Deep Feed-Forward Neural Networks; 1.3.2 Convolutional Neural Networks; 1.3.3 Recurrent Neural Networks; 1.3.4 Training Deep Neural Networks; 1.3.4.1 Loss Functions; 1.3.4.2 Backpropagation; 1.3.4.3 Optimization; 1.3.4.4 Data Sets; 1.3.4.5 Regularization; 1.3.4.6 Training Frameworks
- 1.4 Challenges for Embedded Deep Neural Networks1.5 Book Contributions; References; 2 Optimized Hierarchical Cascaded Processing; 2.1 Introduction; 2.2 Hierarchical Cascaded Systems; 2.2.1 Generalizing Two-Stage Wake-Up Systems; 2.2.2 Hierarchical Cost, Precision, and Recall; 2.2.3 A Roofline Model for Hierarchical Classifiers; 2.2.4 Optimized Hierarchical Cascaded Sensing; 2.3 General Proof of Concept; 2.3.1 System Description; 2.3.2 Input Statistics; 2.3.3 Experiments; 2.3.3.1 Optimal Number of Stages; 2.3.3.2 Optimal Stage Metrics in a Hierarchy; 2.3.4 Conclusion
- 2.4 Case study: Hierarchical, CNN-Based Face Recognition2.4.1 A Face Recognition Hierarchy; 2.4.2 Hierarchical Cost, Precision, and Recall; 2.4.3 An Optimized Face Recognition Hierarchy; 2.5 Conclusion; References; 3 Hardware-Algorithm Co-optimizations; 3.1 An Introduction to Hardware-Algorithm Co-optimization; 3.1.1 Exploiting Network Structure; 3.1.2 Enhancing and Exploiting Sparsity; 3.1.3 Enhancing and Exploiting Fault-Tolerance; 3.2 Energy Gains in Low-Precision Neural Networks; 3.2.1 Energy Consumption of Off-Chip Memory-Access; 3.2.2 Generic Hardware Platform Modeling
- 3.3 Test-Time Fixed-Point Neural Networks3.3.1 Analysis and Experiments; 3.3.2 Influence of Quantization on Classification Accuracy; 3.3.2.1 Uniform Quantization and Per-Layer Rescaling; 3.3.2.2 Per-Layer Quantization; 3.3.3 Energy in Sparse FPNNs; 3.3.4 Results; 3.3.5 Discussion; 3.4 Train-Time Quantized Neural Networks; 3.4.1 Training QNNs; 3.4.1.1 Train-Time Quantized Weights; 3.4.1.2 Train-Time Quantized Activations; 3.4.1.3 QNN Input Layers; 3.4.1.4 Quantized Training; 3.4.2 Energy in QNNs; 3.4.3 Experiments; 3.4.3.1 Benchmarks; 3.4.3.2 QNN Topologies; 3.4.4 Results; 3.4.5 Discussion
- 3.5 Clustered Neural Networks3.6 Conclusion; References; 4 Circuit Techniques for Approximate Computing; 4.1 Introducing the Approximate Computing Paradigm; 4.2 Approximate Computing Techniques; 4.2.1 Resilience Identification and Quality Management; 4.2.2 Approximate Circuits; 4.2.3 Approximate Architectures; 4.2.4 Approximate Software; 4.2.5 Discussion; 4.3 DVAFS: Dynamic-Voltage-Accuracy-Frequency-Scaling; 4.3.1 DVAFS Basics; 4.3.1.1 Introducing the DVAFS Energy-Accuracy Trade-Off; 4.3.1.2 Precision Scaling in DVAFS; 4.3.2 Resilience Identification for DVAFS; 4.3.3 Energy Gains in DVAFS