Verilog HDL design examples /

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Bibliographic Details
Author / Creator:Cavanagh, Joseph, author.
Imprint:Boca Raton, FL : CRC Press, 2017.
Description:1 online resource (xv, 655 pages) : illustrations
Language:English
Subject:
Format: E-Resource Book
URL for this record:http://pi.lib.uchicago.edu/1001/cat/bib/13654119
Hidden Bibliographic Details
ISBN:9781315103846
1315103842
9781351596305
1351596306
9781351596282
1351596284
9781351596299
1351596292
9781138099951
1138099953
Notes:Includes index.
Includes bibliographical references and index.
Print version record.
Summary:The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles--including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs).
Other form:Print version: Cavanagh, Joseph. Verilog HDL design examples. Boca Raton, FL : CRC Press, 2017 9781138099951
Standard no.:10.1201/b22315

MARC

LEADER 00000cam a2200000 i 4500
001 13654119
006 m o d
007 cr cnu---unuuu
008 171020s2017 flu ob 001 0 eng d
005 20241126144640.1
015 |a GBB7G5885  |2 bnb 
016 7 |a 018509804  |2 Uk 
020 |a 9781315103846  |q (electronic bk.) 
020 |a 1315103842  |q (electronic bk.) 
020 |a 9781351596305 
020 |a 1351596306 
020 |a 9781351596282 
020 |a 1351596284 
020 |a 9781351596299  |q (ePub ebook) 
020 |a 1351596292 
020 |z 9781138099951 
020 |z 1138099953 
024 7 |a 10.1201/b22315  |2 doi 
035 9 |a (OCLCCM-CC)1006879226 
035 |a (OCoLC)1006879226 
037 |a 9781351596299  |b Ingram Content Group 
037 |a 9781351596299  |b O'Reilly Media 
040 |a N$T  |b eng  |e rda  |e pn  |c N$T  |d IDEBK  |d YDX  |d EBLCP  |d CNCGM  |d OCLCF  |d OCLCQ  |d UPM  |d U3W  |d OTZ  |d LVT  |d TYFRS  |d S2H  |d OCLCQ  |d UKMGB  |d OCLCQ  |d ZCU  |d OCLCQ  |d OCLCO  |d K6U  |d OCLCQ  |d OCLCO  |d SFB  |d ORMDA  |d OCLCQ  |d OCLCO  |d OCLCL  |d WAU 
049 |a MAIN 
050 4 |a TK7868.D5  |b C3948 2017eb 
072 7 |a TEC  |x 009070  |2 bisacsh 
100 1 |a Cavanagh, Joseph,  |e author. 
245 1 0 |a Verilog HDL design examples /  |c Joseph Cavanagh. 
264 1 |a Boca Raton, FL :  |b CRC Press,  |c 2017. 
300 |a 1 online resource (xv, 655 pages) :  |b illustrations 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
500 |a Includes index. 
588 0 |a Print version record. 
505 0 0 |t Chapter 1 Introduction to Logic Design Using Verilog HDL /  |r Joseph Cavanagh --  |t chapter 2 Combinational Logic Design Using Verilog HDL /  |r Joseph Cavanagh --  |t chapter 3 Sequential Logic Design Using Verilog HDL /  |r Joseph Cavanagh --  |t chapter 4 Computer Arithmetic Design Using Verilog HDL /  |r Joseph Cavanagh. 
520 3 |a The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles--including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs). 
504 |a Includes bibliographical references and index. 
650 0 |a Digital electronics  |x Computer-aided design. 
650 0 |a Logic design.  |0 http://id.loc.gov/authorities/subjects/sh85078117 
650 0 |a Verilog (Computer hardware description language)  |0 http://id.loc.gov/authorities/subjects/sh90004761 
650 6 |a Électronique numérique  |x Conception assistée par ordinateur. 
650 6 |a Structure logique. 
650 6 |a Verilog (Langage de description de matériel informatique) 
650 7 |a TECHNOLOGY & ENGINEERING  |x Mechanical.  |2 bisacsh 
650 7 |a Logic design  |2 fast 
650 7 |a Verilog (Computer hardware description language)  |2 fast 
758 |i has work:  |a Verilog HDL Design Examples (Text)  |1 https://id.oclc.org/worldcat/entity/E39PCXFRX3c6Q8mHjQPFr4YdHy  |4 https://id.oclc.org/worldcat/ontology/hasWork 
776 0 8 |i Print version:  |a Cavanagh, Joseph.  |t Verilog HDL design examples.  |d Boca Raton, FL : CRC Press, 2017  |z 9781138099951  |w (DLC) 2017022734  |w (OCoLC)989045549 
856 4 0 |u https://go.oreilly.com/uchicago/library/view/-/9781351596299/?ar  |y O'Reilly 
929 |a oclccm 
999 f f |s c946a5b0-35f4-4922-84d2-8df3955fbd93  |i 14d43505-1b0d-4d1e-8f89-5beb47972c38 
928 |t Library of Congress classification  |a TK7868.D5C3948 2017eb  |l Online  |c UC-FullText  |u https://go.oreilly.com/uchicago/library/view/-/9781351596299/?ar  |z O'Reilly  |g ebooks  |i 13797058