Computer aided verification : 11th International Conference, CAV'99, Trento, Italy, July 6-10, 1999 ; proceedings /

Computer aided verification : 11th International Conference, CAV'99, Trento, Italy, July 6-10, 1999 ; proceedings /

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Bibliographic Details
Meeting name:CAV'99. Conference (11th : 1999 : Trento, Italy)
Imprint:Berlin ; London : Springer, c1999.
Description:xii, 506 p. : ill. ; 24 cm.
Language:English
Series:Lecture notes in computer science 1633
Subject:
Computer software -- Verification.
Integrated circuits -- Verification.
Conference papers and proceedings.
Format: Print Book
URL for this record:http://pi.lib.uchicago.edu/1001/cat/bib/3854512
Hidden Bibliographic Details
Other authors / contributors:Halbwachs, Nicolas.
Peled, Doron A., 1962-
ISBN:3540662022
Notes:Includes bibliographies and index.

MARC

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245 1 0 |a Computer aided verification :  |b 11th International Conference, CAV'99, Trento, Italy, July 6-10, 1999 ; proceedings /  |c Nicolas Halbwachs, Doron Peled (Eds.) 
260 |a Berlin ;  |a London :  |b Springer,  |c c1999. 
300 |a xii, 506 p. :  |b ill. ;  |c 24 cm. 
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440 0 |a Lecture notes in computer science  |v 1633 
504 |a Includes bibliographies and index. 
505 0 0 |t Alternative Approaches to Hardware Verification /  |r D. L. Dill --  |t The Compositional Specification of Timed Systems - A Tutorial /  |r J. Sifakis --  |t Timed Automata /  |r R. Alur --  |t Stalmarck's Method with Extensions to Quantified Boolean Formulas /  |r G. Stalmarck --  |t Verification of Parameterized Systems by Dynamic Induction on Diagrams /  |r Z. Manna and H. B. Sipma --  |t Formal Methods for Conformance Testing: Theory Can Be Practical! /  |r E. Brinksma --  |t Proof of Correctness of a Processor with Reorder Buffer Using the Completion Functions Approach /  |r R. Hosabettu, M. Srivas and G. Gopalakrishnan --  |t Verifying Safety Properties of a PowerPCMicroprocessor Using Symbolic Model Checking without BDDs /  |r A. Biere, E. Clarke and R. Raimi /  |r [et al.] --  |t Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists /  |r J. Baumgartner, T. Heyman and V. Singhal /  |r [et al.] --  |t Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study /  |r S. Ramesh and P. Bhaduri --  |t Automated Verification of a Parametric Real-Time Program: The ABR Conformance Protocol /  |r B. Berard and L. Fribourg --  |t Test Generation Derived from Model-Checking /  |r T. Jeron and P. Morel --  |t Latency Insensitive Protocols /  |r L. P. Carloni, K. L. McMillan and A. L. Sangiovanni-Vincentelli --  |t Handling Global Conditions in Parametrized System Verification /  |r P. A. Abdulla, A. Bouajjani and B. Jonsson /  |r [et al.] --  |t Verification of Infinite-State Systems by Combining Abstraction and Reachability Analysis /  |r P. A. Abdulla, A. Annichini and S. Bensalem /  |r [et al.] --  |t Experience with Predicate Abstraction /  |r S. Das, D. L. Dill and S. Park --  |t Model Checking of Safety Properties /  |r O. Kupferman and M. Y. Vardi --  |t A Complete Finite Prefix for Process Algebra /  |r R. Langerak and E. Brinksma --  |t The Mathematical Foundation of Symbolic Trajectory Evaluation /  |r C.-T. Chou --  |t Assume-Guarantee Refinement between Different Time Scales /  |r T. A. Henzinger, S. Qadeer and S. K. Rajamani --  |t Efficient Decision Procedures for Model Checking of Linear Time Logic Properties /  |r R. Bloem, K. Ravi and F. Somenzi --  |t Stutter-Invariant Language, [omega]-Automata, and Temporal Logic /  |r K. Etessami --  |t Improved Automata Generation for Linear Temporal Logic /  |r M. Daniele, F. Giunchiglia and M. Y. Vardi --  |t On the Representation of Probabilities over Structured Domains /  |r M. Bozga and O. Maler --  |t Model Checking Partial State Spaces with 3-Valued Temporal Logics /  |r G. Bruns and P. Godefroid --  |t Elementary Microarchitecture Algebra /  |r J. Matthews and J. Launchbury --  |t Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems /  |r T. A. Henzinger, S. Qadeer and S. K. Rajamani --  |t Stepwise CTL Model Checking of State/Event Systems /  |r J. Lind-Nielsen and H. R. Andersen --  |t Optimizing Symbolic Model Checking for Constraint-Rich Models /  |r B. Yang, R. Simmons and R. E. Bryant /  |r [et al.] --  |t Efficient Timed Reachability Analysis Using Clock Difference Diagrams /  |r G. Behrmann, K. G. Larsen and J. Pearson /  |r [et al.] --  |t Mechanizing Proofs of Computation Equivalence /  |r M. Glusman and S. Katz --  |t Linking Theorem Proving and Model-Checking with Well-Founded Bisimulation /  |r P. Manolios, K. S. Namjoshi and R. Sumners --  |t Automatic Verification of Combinational and Pipelined FFT Circuits /  |r P. Bjesse --  |t Efficient Analysis of Cyclic Definitions /  |r K. S. Namjoshi and R. P. Kurshan --  |t A Theory of Restrictions for Logics and Automata /  |r N. Klarlund --  |t Model Checking Based on Sequential ATPG /  |r V. Boppana, S. P. Rajan and K. Takayama /  |r [et al.] --  |t Automatic Verification of Abstract State Machines /  |r M. Spielmann --  |t Abstract and Model Check while You Prove /  |r H. Saidi and N. Shankar --  |t Deciding Equality Formulas by Small Domains Instantiations /  |r A. Pnueli, Y. Rodeh and O. Shtrichman /  |r [et al.] --  |t Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions /  |r R. E. Bryant, S. German and M. N. Velev --  |t A Toolbox for the Analysis of Discrete Event Dynamic Systems /  |r P. Buchholz and P. Kemper --  |t TIPPtool: Compositional Specification and Analysis of Markovian Performance Models /  |r H. Hermanns, V. Mertsiotakis and M. Siegle --  |t Java Bytecode Verification by Model Checking /  |r D. Basin, S. Friedrich and J. Posegga /  |r [et al.] --  |t NuSMV: A New Symbolic Model Verifier /  |r A. Cimatti, E. Clarke and F. Giunchiglia /  |r [et al.] --  |t PIL/SETHEO: A Tool for the Automatic Analysis of Authentication Protocols /  |r J. Schumann. 
650 4 |a Computer software  |x Verification  |v Congresses. 
650 4 |a Integrated circuits  |x Verification  |v Congresses. 
650 7 |a Computer software  |x Verification.  |2 fast  |0 http://id.worldcat.org/fast/fst00872604 
650 7 |a Integrated circuits  |x Verification.  |2 fast  |0 http://id.worldcat.org/fast/fst00975600 
655 7 |a Conference papers and proceedings.  |2 fast  |0 http://id.worldcat.org/fast/fst01423772 
700 1 |a Halbwachs, Nicolas.  |0 http://id.loc.gov/authorities/names/n92101861  |1 http://viaf.org/viaf/167179957 
700 1 |a Peled, Doron A.,  |d 1962-  |0 http://id.loc.gov/authorities/names/n96106229  |1 http://viaf.org/viaf/85346726 
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903 |a HeVa 
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928 |t Library of Congress classification  |a QA76.76.V47C38 1999  |l ASR  |c ASR-SciASR  |i 3674464 
927 |t Library of Congress classification  |a QA76.76.V47C38 1999  |l ASR  |c ASR-SciASR  |e CRERAR  |b 50751690  |i 6300515 
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