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20170719114722.4 |
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010924s2001 caua b 101 0 eng d |
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|a 0769513638
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|a NYCGATR3150-B
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|a (NNC)notisATR3150
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|a (OCoLC)48017042
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|a 90096519
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|a LHL
|c LHL
|d NNC
|d OrLoB-B
|d OCoLC
|d ICU
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|a International Conference on Parallel Architectures and Compilation Techniques
|d (2001 :
|c Barcelona, Catalunya, Spain)
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|a 2001 International Conference on Parallel Architectures and Compilation Techniques :
|b proceedings : 8-12 September, 2001, Barcelona, Catalunya, Spain /
|c sponsored by IEEE Technical Committee on Computer Architecture ... [et al.] ; with the support of Technical University of Catalunya (UPC) ... [et al.]
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|a Proceedings :
|b 2001 International Conference on Parallel Architectures and Compilation Techniques
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|i Additional title on IEEE Computer Society Proceedings list:
|a PACT'01
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|a 2001 International Conference on Parallel Architectures and Compilation Techniques
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| 246 |
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|a International Conference on Parallel Architectures and Compilation Techniques
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| 246 |
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|a Conference on Parallel Architectures and Compilation Techniques
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| 246 |
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|a Parallel Architectures and Compilation Techniques
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|a PACT 2001
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3 |
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|a PACT
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| 260 |
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|a Los Alamitos, California :
|b IEEE Computer Society Press,
|c c2001.
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| 300 |
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|a x, 305 p. :
|b ill. ;
|c 28 cm.
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| 336 |
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|a text
|b txt
|2 rdacontent
|0 http://id.loc.gov/vocabulary/contentTypes/txt
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| 337 |
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|a unmediated
|b n
|2 rdamedia
|0 http://id.loc.gov/vocabulary/mediaTypes/n
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| 338 |
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|a volume
|b nc
|2 rdacarrier
|0 http://id.loc.gov/vocabulary/carriers/nc
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| 500 |
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|a "PACT 2001" -- Cover.
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| 500 |
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|a "IEEE Computer Society Order Number PR01363" -- verso of T.p.
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| 504 |
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|a Includes bibliographic references and author index.
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| 505 |
0 |
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|t Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications /
|r T. Sherwood, E. Perelman and B. Calder --
|t Modeling Supersealar Processors via Statistical Simulation /
|r S. Nussbaum and J. Smith --
|t Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces /
|r L. Eeckhout and K. De Bosschere --
|t Filtering Techniques to Improve Trace-Cache Efficiency /
|r R. Rosner, A. Mendelson and R. Ronen --
|t Reactive-Associative Caches /
|r B. Batson and T. Vijaykumar --
|t Adaptive Mode Control: A Static-Power-Efficient Cache Design /
|r H. Zhou, M. Toburen and E. Rotenberg /
|r [et al.] --
|t Implementation and Evaluation of the Complex Streamed Instruction Set /
|r B. Juurlink, D. Tcheressiz and S. Vassiliadis /
|r [et al.] --
|t On the Efficiency of Reductions in [mu]-SIMD Media Extensions /
|r J. Corbal, R. Espasa and M. Valero --
|t Boolean Formula-Based Branch Prediction for Future Technologies /
|r D. Jimenez, H. Hanson and C. Lin --
|t Using Dataflow Based Context for Accurate Value Prediction /
|r R. Thomas and M. Franklin --
|t Recovery Mechanism for Latency Misprediction /
|r E. Morancho, J. Maria Llaberia and A. Olive --
|t A Cost Framework for Evaluating Integrated Restructuring Optimizations /
|r B. Chandramouli, J. Carter and W. Hsieh /
|r [et al.] --
|t Compiling for the Impulse Memory Controller /
|r X. Huang, Z. Wang and K. McKinley --
|t On the Stability of Temporal Data Reference Profiles /
|r T. Chilimbi --
|t Code Reordering and Speculation Support for Dynamic Optimization Systems /
|r E. Nystrom, R. Barnes and M. Merten /
|r [et al.] --
|t A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors /
|r J. Codina, J. Sanchez and A. Gonzalez --
|t Cache-Friendly Implementations of Transitive Closure /
|r M. Penner and V. Prasanna --
|t Exploring the Design Space of Future CMPs /
|r J. Huh, D. Burger and S. Keckler --
|t Area and System Clock Effects on SMT/CMP Processors /
|r J. Burns and J.-L. Gaudiot --
|t Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms /
|r F. Warg and P. Stenstrom --
|t Compiler and Runtime Analysis for Efficient Communication in Data Intensive Applications /
|r R. Ferreira, G. Agrawal and J. Saltz --
|t Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors /
|r M. Garzaran, M. Prvulovic and Y. Zhang /
|r [et al.] --
|t Optimizing Software Data Prefetches with Rotating Registers /
|r G. Doshi, R. Krishnaiyer and K. Muthukumar --
|t Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes /
|r N. Kohout, S. Choi and D. Kim /
|r [et al.] --
|t Data Flow Analysis for Software Prefetching Linked Data Structures in Java /
|r B. Cahoon and K. McKinley --
|t Comparing and Combining Read Miss Clustering and Software Prefetching /
|r V. Pai and S. Adve.
|
| 530 |
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|a Also available via the World Wide Web with additional title: Parallel Architectures and Compilation Techniques, 2001, proceedings, 2001 International Conference on.
|
| 650 |
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0 |
|a Parallel computers
|v Congresses.
|0 http://id.loc.gov/authorities/subjects/sh2008108873
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| 650 |
|
0 |
|a Computer architecture
|v Congresses.
|0 http://id.loc.gov/authorities/subjects/sh2008101468
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| 650 |
|
0 |
|a Parallel processing (Electronic computers)
|v Congresses.
|0 http://id.loc.gov/authorities/subjects/sh2008108874
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| 650 |
|
0 |
|a Compiling (Electronic computers)
|v Congresses.
|
| 650 |
|
0 |
|a Compilers (Computer programs)
|v Congresses.
|0 http://id.loc.gov/authorities/subjects/sh2008117721
|
| 650 |
|
7 |
|a Compilers (Computer programs)
|2 fast
|0 http://id.worldcat.org/fast/fst00871538
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| 650 |
|
7 |
|a Compiling (Electronic computers)
|2 fast
|0 http://id.worldcat.org/fast/fst00871540
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| 650 |
|
7 |
|a Computer architecture.
|2 fast
|0 http://id.worldcat.org/fast/fst00872026
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| 650 |
|
7 |
|a Parallel computers.
|2 fast
|0 http://id.worldcat.org/fast/fst01052922
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| 650 |
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|a Parallel processing (Electronic computers)
|2 fast
|0 http://id.worldcat.org/fast/fst01052928
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| 655 |
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|a Conference papers and proceedings.
|2 fast
|0 http://id.worldcat.org/fast/fst01423772
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| 710 |
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|a IEEE Computer Society.
|b Technical Committee on Computer Architecture.
|0 http://id.loc.gov/authorities/names/n81088642
|1 http://viaf.org/viaf/134878713
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| 710 |
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|a Universitat Polit�cnica de Catalunya
|0 http://id.loc.gov/authorities/names/n86106152
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| 740 |
0 |
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|a Parallel Architectures and Compilation Techniques, 2001, proceedings, 2001 International Conference on.
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| 856 |
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|t Library of Congress classification
|a QA76.58 .I5445 2001
|l JCL
|c JCL-Sci
|i 4532153
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