Software and Compilers for Embedded Systems : 8th International Workshop, SCOPES 2004, Amsterdam, The Netherlands, September 2-3, 2004, Proceedings /
Saved in:
| Author / Creator: | Schepers, Henk. |
|---|---|
| Imprint: | Berlin, Heidelberg : Springer Berlin Heidelberg, 2004. |
| Language: | English |
| Series: | Lecture notes in computer science, 0302-9743 ; 3199 |
| Subject: | |
| Format: | E-Resource |
| URL for this record: | http://pi.lib.uchicago.edu/1001/cat/bib/7354468 |
Table of Contents:
- Invited Talk
- The New Economics of Embedded Systems
- Application Specific (Co)Design
- A Framework for Architectural Description of Embedded System
- Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units
- ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study
- System and Application Synthesis
- Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition
- An Integer Linear Programming Approach to Classify the Communication in Process Networks
- Predictable Embedded Multiprocessor System Design
- Data Flow Analysis
- Suppression of Redundant Operations in Reverse Compiled Code Using Global Dataflow Analysis
- Fast Points-to Analysis for Languages with Structured Types
- Data Partitioning
- An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications
- Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization
- On the Phase Coupling Problem Between Data Memory Layout Generation and Address Pointer Assignment
- Task Scheduling
- Dynamic Mapping and Ordering Tasks of Embedded Real-Time Systems on Multiprocessor Platforms
- Integrated Intra- and Inter-task Cache Analysis for Preemptive Multi-tasking Real-Time Systems
- A Fuzzy Adaptive Algorithm for Fine Grained Cache Paging
- Code Generation
- DSP Code Generation with Optimized Data Word-Length Selection
- Instruction Selection for Compilers that Target Architectures with Echo Instructions
- A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor
- Author Index