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|a (OCoLC)209915472
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|a 978-0-387-29221-2
|b Springer
|n http://www.springerlink.com
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|a Bergeron, Janick.
|0 http://id.loc.gov/authorities/names/n99252864
|1 http://viaf.org/viaf/65804529
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1 |
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|a Writing testbenches using System Verilog /
|c by Janick Bergeron.
|
| 250 |
|
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|a [Rev. ed.].
|
| 260 |
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|a New York :
|b Springer Science+Business Media,
|c c2006.
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| 300 |
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|a 1 online resource (xxvi, 412 p.) :
|b ill.
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|a text
|b txt
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|a This book presents the same concepts as the second edition published with title, Writing testbenches, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.
|
| 500 |
|
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|a Includes index.
|
| 504 |
|
|
|a Includes bibliographical references and index.
|
| 588 |
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|a Description based on print version record.
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0 |
|a Verilog (Computer hardware description language)
|0 http://id.loc.gov/authorities/subjects/sh90004761
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|a Integrated circuits
|x Verification.
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| 650 |
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|a Circuit intégré
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| 650 |
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|a Verilog (Langage de description de matériel informatique)
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|a Electronic books.
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|a Integrated circuits
|x Verification.
|2 fast
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| 650 |
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|a Verilog (Computer hardware description language)
|2 fast
|0 http://id.worldcat.org/fast/fst01165388
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|a Writing testbenches.
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|i Print version:
|a Bergeron, Janick.
|t Writing testbenches using System Verilog.
|b [Rev. ed.].
|d New York : Springer Science+Business Media, c2006
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