The power of assertions in SystemVerilog /

The power of assertions in SystemVerilog /

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Bibliographic Details
Imprint:	New York ; London : Springer, c2010.
Description:	1 online resource (xvii, 544 p.) : ill.
Language:	English
Subject:	Verilog (Computer hardware description language) Integrated circuits -- Verification -- Data processing. Integrated circuits -- Verification -- Data processing. Verilog (Computer hardware description language)
Format:	E-Resource Book
URL for this record:	http://pi.lib.uchicago.edu/1001/cat/bib/8896345

Hidden Bibliographic Details
Other authors / contributors:	Cerny, Eduard.
ISBN:	9781441966001 (electronic bk.) 1441966005 (electronic bk.) 9781441965998 1441965998
Notes:	Includes bibliographical references (p. 535-537) and index. Available also in a print ed. Mode of access: World Wide Web. Description based on print version record.
Other form:	Print version: Power of assertions in SystemVerilog. New York ; London : Springer, 2010 9781441965998

Description
Summary:	This book is the result of the deep involvementof the authors in the development of EDA tools, SystemVerilog Assertion standardization, and many years of practical experience. One of the goals of this book is to expose the oral knowhow circulated among design and veri?cation engineers which has never been written down in its full extent. The book thus contains many practical examples and exercises illustr- ing the various concepts and semantics of the assertion language. Much attention is given to discussing ef?ciency of assertion forms in simulation and formal veri?- tion. We did our best to validate all the examples, but there are hundreds of them and not all features could be validated since they have not yet been implemented in EDA tools. Therefore, we will be grateful to readers for pointing to us any needed corrections. The book is written in a way that we believe serves well both the users of SystemVerilog assertions in simulation and also those who practice formal v- i?cation (model checking). Compared to previous books covering SystemVerilog assertions we include in detail the most recent features that appeared in the IEEE 1800-2009 SystemVerilog Standard, in particular the new encapsulation construct "checker" and checker libraries, Linear Temporal Logic operators, semantics and usage in formal veri?cation. However, for integral understanding we present the assertion language and its applications in full detail. The book is divided into three parts.
Physical Description:	1 online resource (xvii, 544 p.) : ill.
Format:	Mode of access: World Wide Web.
Bibliography:	Includes bibliographical references (p. 535-537) and index.
ISBN:	9781441966001 1441966005 9781441965998 1441965998