Fault tolerant architectures for cryptography and hardware security /

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Bibliographic Details
Imprint:Singapore : Springer, [2018]
Description:1 online resource (xii, 240 pages)
Language:English
Series:Computer architecture and design methodologies
Computer architecture and design methodologies.
Subject:
Format: E-Resource Book
URL for this record:http://pi.lib.uchicago.edu/1001/cat/bib/11544221
Hidden Bibliographic Details
Other authors / contributors:Patranabis, Sikhar, editor.
Mukhopadhyay, Debdeep, editor.
ISBN:9789811013874
981101387X
9789811013867
9811013861
Digital file characteristics:text file
PDF
Notes:Includes bibliographical references.
Online resource; title from PDF title page (SpringerLink, viewed April 3, 2018).
Summary:This book uses motivating examples and real-life attack scenarios to introduce readers to the general concept of fault attacks in cryptography. It offers insights into how the fault tolerance theories developed in the book can actually be implemented, with a particular focus on a wide spectrum of fault models and practical fault injection techniques, ranging from simple, low-cost techniques to high-end equipment-based methods. It then individually examines fault attack vulnerabilities in symmetric, asymmetric and authenticated encryption systems. This is followed by extensive coverage of countermeasure techniques and fault tolerant architectures that attempt to thwart such vulnerabilities. Lastly, it presents a case study of a comprehensive FPGA-based fault tolerant architecture for AES-128, which brings together of a number of the fault tolerance techniques presented. It concludes with a discussion on how fault tolerance can be combined with side channel security to achieve protection against implementation-based attacks. The text is supported by illustrative diagrams, algorithms, tables and diagrams presenting real-world experimental results.
Other form:Printed edition: 9789811013867
Standard no.:10.1007/978-981-10-1387-4