Hidden Bibliographic Details
| Varying Form of Title: | Architectures and circuits for modern wireless and wireline systems
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| Other authors / contributors: | Rhee, Woogeun, 1968- editor.
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| ISBN: | 9781785618864
1785618865
1785618857
9781785618857
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| Notes: | Includes bibliographical references and index (pages 697-715).
Online resource; title from PDF title page (IET Digital, viewed June 9, 2020).
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| Summary: | The book has 25 chapters and is divided into 5 parts. The first part which is about Basic architectures and system perspectives deals with Evolution of monolithic phase-locked loops; Fractional-N frequency synthesis; Clock data recovery: a system perspective; and Silicon-based THz frequency synthesizers with wide locking range. The second part which is about Digital-intensive phase-locked loops covers Time-to-digital converters; Bang-bang digital PLLs for wireless systems; Hybrid PLLs; Spur mitigation techniques for DPLL architecture; Fully synthesized digital PLL; and Ultra-low-power ADPLL. The third part which is about Low-noise frequency generation and modulation covers Integrated LC oscillators; Mm-wave and sub-THz CMOS VCOs; Ultra-low phase noise ADPLL for millimeter wave; DTC-based subsampling PLLs for low-noise synthesis and two-point modulation; and Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering. The fourth part which is about Clock-and-data recovery and clocking covers An overview of CDR in ultra-high-speed wireline transceivers; Clock and data recovery for optical links; Digital clock and data recovery circuits; Spread spectrum clock generator: a low-cost EMI solution; and High-performance CMOS clock distribution. Finally, part five which is about Advanced clock/frequency generation deals with Sub-sampling PLL techniques; PLLs with nested frequency-locked loop; Time amplified charge pump PLL; Multiplying DLLs; and Wideband PLLs.
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| Other form: | Print version: Phase-locked frequency generation and clocking. [S.l.] : INST OF ENGIN AND TECH, 2020 1785618857
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