On-chip networks /

On-chip networks /

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Bibliographic Details
Author / Creator:Enright Jerger, Natalie D.
Imprint:San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2009.
Description:1 electronic text (xii, 127 p. : ill.) : digital file.
Language:English
Series:Synthesis lectures on computer architecture, 1935-3243 ; # 8
Synthesis lectures on computer architecture (Online), # 8.
Subject:
Networks on a chip.
Networks on a chip.
Format: E-Resource Book
URL for this record:http://pi.lib.uchicago.edu/1001/cat/bib/8512720
Hidden Bibliographic Details
Other authors / contributors:Peh, Li-Shiuan.
ISBN:9781598295856 (electronic bk.)
9781598295849 (pbk.)
Notes:Title from PDF t.p. (viewed on August 9, 2009).
Series from website.
Includes bibliographical references (p. 105-125).
Abstract freely available; full-text restricted to subscribers or individual document purchasers.
Also available in print.
Mode of access: World Wide Web.
System requirements: Adobe Acrobat reader.
Summary:With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field.
Standard no.:10.2200/S00209ED1V01Y200907CAC008

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