Hidden Bibliographic Details
| Other authors / contributors: | Thornton, Mitchell Aaron.
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| ISBN: | 1598291076 (electronic bk.)
9781598291070 (electronic bk.)
1598291068 (pbk.)
9781598291063 (pbk.)
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| Notes: | Series from website.
Title from PDF t.p. (viewed on October 11, 2008).
Includes bibliographical references (p. 73).
Abstract freely available; full-text restricted to subscribers or individual document purchasers.
Also available in print.
System requirements: Adobe Acrobat Reader.
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| Summary: | Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system net lists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is any one with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. This book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.
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| Standard no.: | 10.2200/S00060ED1V01Y200610DCS006
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