Hidden Bibliographic Details
| Other authors / contributors: | Zhang, Yaowen.
Chen, Sao-Jie.
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| ISBN: | 9781402061950
1402061951
9781402061943
1402061943
9786611066505
6611066500
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| Notes: | Includes bibliographical references (p. 95-102).
Description based on print version record.
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| Summary: | At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting.
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| Other form: | Print version: Ho, Tsung-Yi. Full-chip nanometer routing techniques. Dordrecht : Springer, c2007 9781402061943 1402061943
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