The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits : the semi-empirical and compact model approaches /

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Bibliographic Details
Author / Creator:	Jespers, Paul G.
Imprint:	Dordrecht ; New York : Springer, c2010.
Description:	1 online resource (xvi, 171 p.) : ill.
Language:	English
Series:	Analog circuits and signal processing Analog Circuits and Signal Processing Series.
Subject:	Metal oxide semiconductors, Complementary -- Design and construction. Low voltage integrated circuits -- Design and construction. Linear integrated circuits -- Design and construction. Linear integrated circuits -- Design and construction. Low voltage integrated circuits -- Design and construction. Metal oxide semiconductors, Complementary -- Design and construction.
Format:	E-Resource Book
URL for this record:	http://pi.lib.uchicago.edu/1001/cat/bib/8893720

Hidden Bibliographic Details
ISBN:	9780387471013 (e-isbn) 0387471014 (e-isbn) 9780387471006 0387471006
Notes:	In title "gm/ID" both the m and D are subscript. Includes bibliographical references (p. 167-168) and index. Description based on print version record.
Other form:	Print version: Jespers, Paul G. Gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits. Dordrecht ; London ; New York : Springer, 2010 9780387471006

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